1. Field of the Invention
This invention relates to memory subsystems and, more particularly, to contact pad arrangement on memory modules.
2. Description of the Related Art
The demand for performance in computer systems is continually increasing. There are many methods of increasing the performance of a computer system. One method for increasing performance is to increase the size of the memory. This is true for all levels within the memory hierarchy, including registers (within a microprocessor core), cache memory, main memory, and disk storage. In many cases, an increase in the size the main memory will result in a significant performance gain by a computer system.
Another method of increasing the performance of a computer system may be to increase the clock speed of the microprocessor and associated system buses. Other methods of increasing the speed of computer systems involve architectural changes, which may be implemented in the design phase of a computer system. One such architectural change is to increase the size of the data bus. Increasing the size of the data bus may allow computers to process more information per clock cycle than computers with smaller data buses. For example, a computer with a 32-bit data bus may be able to process twice as much information per clock cycle as a computer with a 16-bit data bus.
Although increasing the size of the data bus and the clock speed of a computer system are two methods of obtaining higher performance, these methods may have an adverse impact on the performance of memory modules. Memory modules have been used for some time as a computer""s main memory, since their modularity may make memory reconfiguration easier. Memory modules may also make removing and replacing faulty memory segments easier.
Memory modules are typically implemented using small circuit boards with limited area for signal traces and contact pads. Implementing a larger data bus can present significant difficulties in designing a circuit board for a memory module intended for such computer systems. In addition to traces and contact pads for the data bus, area must be reserved for traces and contact pads necessary to convey address and control signals to the chips on the module, as well as for power and ground connections. Thus, as more traces and contact pads are added to a given circuit board, the closer the traces and contact pads may be placed to each other. As traces and contact pads are moved closer together signal integrity may be compromised due to inter-electrode capacitance and other proximity related interference. This type of interference is sometimes referred to as xe2x80x9ccross-talk.xe2x80x9d Such cross-talk may induce errors into signal lines on a memory module or computer motherboard.
Increasing the clock speed of a computer system may further increase interference problems caused by signal traces and contact pads that are close together. Typically, as the speed of operation increases, the potential for cross-talk between the various signals may also increase. In some cases, an error correction subsystem may be able to correct these errors. However, typical error correction subsystems are limited in the number of simultaneous errors they may detect and/or correct. Uncorrected errors may often times lead to undesirable operation of a computer system. Memory modules operating at higher clock speeds with large data bus widths may be especially susceptible to errors induced by cross-talk.
Various embodiments of a memory module having balanced data input and output contacts are disclosed. In one embodiment, a memory module includes a printed circuit board having an edge connector and a plurality of memory integrated circuits. The edge connector may be adapted for insertion into a socket of a motherboard of a computer system, for example. The edge connector includes a plurality of contact pads on both sides of the printed circuit board. The contact pads are configured to convey data signals, power and ground to and from the printed circuit board. The power and ground contact pads alternate along the edge connector. There are no more than four data signal contact pads without intervening power or ground contact pads.
In one particular implementation, the memory integrated circuits (ICs) are synchronous dynamic random access memories (SDRAM). In another implementation, the memory ICs are dynamic random access memories (DRAM).
In other implementations, the memory ICs are arranged on the printed circuit board to minimize the trace length between a particular memory chip and corresponding contact pads associated with the particular memory chip.